The process of creating very-large-scale integrated (VLSI) circuit designs typically includes a structured sequence of steps. In an initial step, a VLSI circuit designer creates a computerized representation of a VLSI circuit design using a computerized tool. In the ensuing steps, the designer generates a series of subsequent representations using specialized tools including synthesis tools, optimization tools, and place-and-route tools. The designer might also generate a new representation manually using a computerized editing tool.
In general, each representation in the series describes the design at a different level of abstraction. It is common for the initial representation to describe the design at a high level of abstraction, and for each subsequent representation to describe the design at a respective lower level of abstraction. For example, the initial representation may describe the design at the register-transfer level (RTL), a subsequent representation may describe the design at the gate-level, and a subsequent representation from that may describe the design at the transistor-level. The process culminates with the generation of a database containing geometric detail of masks that will be used to fabricate the design.
A circuit design representation describes a design as a set of basic components or elements that are connected together. Due to the size and complexity of VLSI circuit designs, it is a common practice for the designer to group elements together in subsets called module definitions (or modules). A module defines an arrangement of elements and other modules, and can be instantiated more than once in a representation. That is, the designer creates a module once to define an arrangement of elements, and uses instances of that module to represent specific portions of the design. Many hardware description languages (HDLs) support this hierarchical manner of design description. Designs are written as a set of module definitions. Computerized tools that read such designs can construct the full hierarchical representation of the design from the module definitions. In the full hierarchical representation, each element of the design has a unique representation.
To insure that no unintended changes are introduced into a newly generated representation, particularly when manual modifications have been made, the designer applies a computerized verification tool to the newly generated representation and its predecessor. The verification tool verifies that particular design aspects such as functional behaviors are preserved from representation to representation. This verifying process commonly is referred to as "design verification." An example of such a tool is Design VERIFYer, which is marketed by Chrysalis Symbolic Design, Inc. of Billerica, Mass. Design VERIFYer verifies behavior preservation between first and second representations of a circuit design by finding matches between signals represented by the representations, and comparing the logic functions driving the signals.
The signals of each representation are identifiable by signal name. If two representations are at the same level of abstraction (e.g., before and after optimization at the gate level) the signal names typically are kept the same. Design VERIFYer has a "name based" mode that finds matches between signals of different representations by matching signal names.
If two representations are at different levels of abstraction (e.g., before and after RTL-to-gate synthesis) the signal names typically are changed in some uniform manner. It is common for a designer to use a signal name mapping tool that performs "rule-based signal matching"prior to running the design verification tool to account for such changes. The signal name matching tool refers to each signal in the representation by signal name, i.e., by a character string. The character string is a series of subnames separated by a delimiter ".". The last subname in the series uniquely identifies a signal within a particular element of the representation. The portion of the series up to but not including the last subname uniquely identifies the element within the representation that contains the signal.
Mapping rules describe how the signal names have changed from the first representation to the second representation. Each mapping rule consists of a keyword, a first subrule and a second subrule. The keyword indicates to the tool that the instruction is a mapping rule. The first subrule matches with signal names of the first representation, and the second subrule matches with signal names of the second representation. Each subrule includes one or more fields. A field can be a literal field that matches with a portion of a signal name character for character. Alternatively, a field can be a match field that matches with a portion of a name in a manner similar to that of %s or %d in scanf of the C programming language. The match fields of the first and second subrule are linked so that the same character string is matched by each match field.
The operation of the rule-based signal matching tool will now be described in further detail. First, the tool selects a mapping rule from the designer provided set of rules, and applies the mapping rule to a signal name of the first representation. In particular, the tool attempts to match the signal name with the first subrule. If the attempt is successful, i.e., if the signal name of the first representation matches the first subrule, the tool generates a signal name description according to the second subrule and the signal name that matches the first subrule. The tool then searches the second representation for a signal name fitting the signal name description. If the tool finds a signal name of the second representation matching the description, the tool stores the signal name of the first representation with the signal name of the second representation in a file as a mapped pair of signal names. The tool then applies the mapping rule to another signal name of the first representation, and repeats the generating/searching steps if the new name matches the first subrule. When the tool has applied the rule to all signal names of the first representation, the tool selects another mapping rule and applies it to signals of the first representation. When all mapping rules have been applied, the tool is finished. The design verification tool reads the mapped pairs of signal names from the file, and uses them to compare the first and second representations.
By way of example, suppose a design includes a clock signal and an instance of an input-output module. Additionally, the input-output module includes an acknowledge signal and two instances of a datapath module. Furthermore, each datapath module includes an output signal. In a first representation, the design has name "A", the clock signal has name "clk", the input-output module instance has name "IO", the acknowledge signal has name "ack", the first datapath module instance has name "DP1", the second datapath module instance has name "DP2", and the output signal has name "out". The full names (i.e., the design name, any module instance names, and the signal name, each name being delimited by ".") of the four signals are:
"A.clk" PA1 "A.IO.ack" PA1 "A.IO.DP1.out" PA1 "A.IO.DP2.out" PA1 "B.clk" PA1 "B.I_IO.ack" PA1 "B.I_IO.I_DP1.out" PA1 "B.I_IO.I_DP2.out"
In a second representation, the design has name "B", the input-output module instance has name "I_IO", the first datapath module instance has name "I_DP1", the second datapath module instance has name "I_DP2", and the signal names of the second representation have the same names as those of the first representation. The full names of the four signals are:
In this example, the computerized tool that was used to produce the second representation from the first representation added the prefix "I_" to the names of the module instances of the first representation to generate the names of the module instances of the second representation.
The rule-based signal matching tool tries to match signal names of the first representation with signal names of the second representation. Since the signal names of the representations are different (by the "I_" prefix used in the second representation), the designer provides the tool with a set of mapping rules. In particular, to match the signal names "A.clk" and "B.clk", the designer provides the mapping rule: EQU map_signals A.%s B.%s (1)
Here, "map_signals" is a keyword indicating that the instruction is a mapping rule. Each subrule includes a literal field and a match field. The first subrule includes "A." as its literal field, and "%s" as its match field. Similarly, the second subrule includes "B." as its literal field and "%s" as its match field. The match fields of the first and second subrules are linked so that the same character string is matched by both fields.
When the tool gets the signal name "A.clk" and applies mapping rule (1), the literal field "A." of the first subrule matches character for character with the "A." portion of the signal name, and the match field "%s" of the first subrule matches with the "clk" portion of the signal name. Accordingly, the tool generates a signal name description according to the subject signal name "A.clk" and the second subrule of mapping rule (1). In particular, the second subrule has a literal field "B." followed by a match field "%s" such that the description begins with the characters "B." and ends with characters from the link between the match fields of the first and second subrules, namely "clk". Accordingly, the generated description is "B.clk". The tool searches the second representation and finds that a signal name "B.clk" exists in the second representation. Accordingly, the tool has successfully matched the signal names "A.clk" and "B.clk". The tool then adds the pair of matched signal names to a line entry in a initial mapping file as part of the initial mapping.
An example of a conventional signal name matching tool is GENMAP, which is developed by Chrysalis Symbolic Design, Inc. for use in conjunction with Design VERIFYer. GENMAP generates an initial mapping file, and Design VERIFYer uses the initial mapping file to verify behavior preservation.